snes9x/apu/bapu/smp/core/oppseudo_mov.cpp

case 0x7d: {
  op_io();
  regs.endian.a = regs.x;
  regs.p.n = !!(regs.endian.a & 0x80);
  regs.p.z = (regs.endian.a == 0);
  break;
}

case 0xdd: {
  op_io();
  regs.endian.a = regs.endian.y;
  regs.p.n = !!(regs.endian.a & 0x80);
  regs.p.z = (regs.endian.a == 0);
  break;
}

case 0x5d: {
  op_io();
  regs.x = regs.endian.a;
  regs.p.n = !!(regs.x & 0x80);
  regs.p.z = (regs.x == 0);
  break;
}

case 0xfd: {
  op_io();
  regs.endian.y = regs.endian.a;
  regs.p.n = !!(regs.endian.y & 0x80);
  regs.p.z = (regs.endian.y == 0);
  break;
}

case 0x9d: {
  op_io();
  regs.x = regs.sp;
  regs.p.n = !!(regs.x & 0x80);
  regs.p.z = (regs.x == 0);
  break;
}

case 0xbd: {
  op_io();
  regs.sp = regs.x;
  break;
}

case 0xe8: {
  regs.endian.a = op_readpc();
  regs.p.n = !!(regs.endian.a & 0x80);
  regs.p.z = (regs.endian.a == 0);
  break;
}

case 0xcd: {
  regs.x = op_readpc();
  regs.p.n = !!(regs.x & 0x80);
  regs.p.z = (regs.x == 0);
  break;
}

case 0x8d: {
  regs.endian.y = op_readpc();
  regs.p.n = !!(regs.endian.y & 0x80);
  regs.p.z = (regs.endian.y == 0);
  break;
}

case 0xe6: {
  switch(++opcode_cycle) {
  case 1:
    op_io();
    break;
  case 2:
    regs.endian.a = op_readdp(regs.x);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xbf: {
  switch(++opcode_cycle) {
  case 1:
    op_io();
    break;
  case 2:
    regs.endian.a = op_readdp(regs.x++);
    op_io();
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xe4: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    break;
  case 2:
    regs.endian.a = op_readdp(sp);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xf8: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    break;
  case 2:
    regs.x = op_readdp(sp);
    regs.p.n = !!(regs.x & 0x80);
    regs.p.z = (regs.x == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xeb: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    break;
  case 2:
    regs.endian.y = op_readdp(sp);
    regs.p.n = !!(regs.endian.y & 0x80);
    regs.p.z = (regs.endian.y == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xf4: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    op_io();
    break;
  case 2:
    regs.endian.a = op_readdp(sp + regs.x);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xf9: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    op_io();
    break;
  case 2:
    regs.x = op_readdp(sp + regs.endian.y);
    regs.p.n = !!(regs.x & 0x80);
    regs.p.z = (regs.x == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xfb: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    op_io();
    break;
  case 2:
    regs.endian.y = op_readdp(sp + regs.x);
    regs.p.n = !!(regs.endian.y & 0x80);
    regs.p.z = (regs.endian.y == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xe5: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    break;
  case 2:
    sp |= op_readpc() << 8;
    break;
  case 3:
    regs.endian.a = op_readaddr(sp);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xe9: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    sp |= op_readpc() << 8;
    break;
  case 2:
    regs.x = op_readaddr(sp);
    regs.p.n = !!(regs.x & 0x80);
    regs.p.z = (regs.x == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xec: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    sp |= op_readpc() << 8;
    break;
  case 2:
    regs.endian.y = op_readaddr(sp);
    regs.p.n = !!(regs.endian.y & 0x80);
    regs.p.z = (regs.endian.y == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xf5: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    sp |= op_readpc() << 8;
    op_io();
    break;
  case 2:
    regs.endian.a = op_readaddr(sp + regs.x);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xf6: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    sp |= op_readpc() << 8;
    op_io();
    break;
  case 2:
    regs.endian.a = op_readaddr(sp + regs.endian.y);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xe7: {
  switch(++opcode_cycle) {
  case 1:
    dp = op_readpc() + regs.x;
    op_io();
    break;
  case 2:
    sp  = op_readdp(dp);
    break;
  case 3:
    sp |= op_readdp(dp + 1) << 8;
    break;
  case 4:
    regs.endian.a = op_readaddr(sp);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xf7: {
  switch(++opcode_cycle) {
  case 1:
    dp = op_readpc();
    op_io();
    break;
  case 2:
    sp  = op_readdp(dp);
    break;
  case 3:
    sp |= op_readdp(dp + 1) << 8;
    break;
  case 4:
    regs.endian.a = op_readaddr(sp + regs.endian.y);
    regs.p.n = !!(regs.endian.a & 0x80);
    regs.p.z = (regs.endian.a == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xfa: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    break;
  case 2:
    rd = op_readdp(sp);
    break;
  case 3:
    dp = op_readpc();
    break;
  case 4:
    op_writedp(dp, rd);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0x8f: {
  switch(++opcode_cycle) {
  case 1:
    rd = op_readpc();
    dp = op_readpc();
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, rd);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xc6: {
  switch(++opcode_cycle) {
  case 1:
    op_io();
    break;
  case 2:
    op_readdp(regs.x);
    break;
  case 3:
    op_writedp(regs.x, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xaf: {
  switch(++opcode_cycle) {
  case 1:
    op_io(2);
  case 2:
    op_writedp(regs.x++, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xc4: {
  switch(++opcode_cycle) {
  case 1:
    dp = op_readpc();
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xd8: {
  switch(++opcode_cycle) {
  case 1:
    dp = op_readpc();
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, regs.x);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xcb: {
  switch(++opcode_cycle) {
  case 1:
    dp = op_readpc();
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, regs.endian.y);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xd4: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    op_io();
    dp += regs.x;
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xd9: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    op_io();
    dp += regs.endian.y;
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, regs.x);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xdb: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    op_io();
    dp += regs.x;
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp, regs.endian.y);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xc5: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    break;
  case 2:
    dp |= op_readpc() << 8;
    break;
  case 3:
    op_readaddr(dp);
    break;
  case 4:
    op_writeaddr(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xc9: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    break;
  case 2:
    dp |= op_readpc() << 8;
    break;
  case 3:
    op_readaddr(dp);
    break;
  case 4:
    op_writeaddr(dp, regs.x);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xcc: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    break;
  case 2:
    dp |= op_readpc() << 8;
    break;
  case 3:
    op_readaddr(dp);
    break;
  case 4:
    op_writeaddr(dp, regs.endian.y);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xd5: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    dp |= op_readpc() << 8;
    op_io();
    dp += regs.x;
    break;
  case 2:
    op_readaddr(dp);
    break;
  case 3:
    op_writeaddr(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xd6: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    dp |= op_readpc() << 8;
    op_io();
    dp += regs.endian.y;
    break;
  case 2:
    op_readaddr(dp);
    break;
  case 3:
    op_writeaddr(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xc7: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    op_io();
    sp += regs.x;
    break;
  case 2:
    dp  = op_readdp(sp);
    break;
  case 3:
    dp |= op_readdp(sp + 1) << 8;
    break;
  case 4:
    op_readaddr(dp);
    break;
  case 5:
    op_writeaddr(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xd7: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    break;
  case 2:
    dp  = op_readdp(sp);
    break;
  case 3:
    dp |= op_readdp(sp + 1) << 8;
    op_io();
    dp += regs.endian.y;
    break;
  case 4:
    op_readaddr(dp);
    break;
  case 5:
    op_writeaddr(dp, regs.endian.a);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xba: {
  switch(++opcode_cycle) {
  case 1:
    sp = op_readpc();
    break;
  case 2:
    regs.endian.a = op_readdp(sp);
    op_io();
    break;
  case 3:
    regs.endian.y = op_readdp(sp + 1);
    regs.p.n = !!(regs.ya & 0x8000);
    regs.p.z = (regs.ya == 0);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xda: {
  switch(++opcode_cycle) {
  case 1:
    dp = op_readpc();
    break;
  case 2:
    op_readdp(dp);
    break;
  case 3:
    op_writedp(dp,     regs.endian.a);
    break;
  case 4:
    op_writedp(dp + 1, regs.endian.y);
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xaa: {
  switch(++opcode_cycle) {
  case 1:
    sp  = op_readpc();
    sp |= op_readpc() << 8;
    break;
  case 2:
    bit = sp >> 13;
    sp &= 0x1fff;
    rd = op_readaddr(sp);
    regs.p.c = !!(rd & (1 << bit));
    opcode_cycle = 0;
    break;
  }
  break;
}

case 0xca: {
  switch(++opcode_cycle) {
  case 1:
    dp  = op_readpc();
    dp |= op_readpc() << 8;
    break;
  case 2:
    bit = dp >> 13;
    dp &= 0x1fff;
    rd = op_readaddr(dp);
    if(regs.p.c)rd |=  (1 << bit);
    else        rd &= ~(1 << bit);
    op_io();
    break;
  case 3:
    op_writeaddr(dp, rd);
    opcode_cycle = 0;
    break;
  }
  break;
}