490 lines
12 KiB
C
490 lines
12 KiB
C
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/*++
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Copyright (c) 2000-2001 Microsoft Corporation
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Module Name:
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shpc.h
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Abstract:
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Type definitions describing a Standard Hotplug Controller
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Author:
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Davis Walker (dwalker) 10 October 2000
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Revision History:
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--*/
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#ifndef _SHPC_
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#define _SHPC_
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#include "pshpack1.h"
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//
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// Register set structures
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//
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//
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// Slots Available Registers
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//
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// This is a two DWORD structure.
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//
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typedef struct _SHPC_SLOTS_AVAILABLE_REGISTER {
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ULONG NumSlots33Conv:5; // HWINIT
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ULONG:3; // RsvdP
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ULONG NumSlots66PciX:5; // HWINIT
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ULONG:3; // RsvdP
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ULONG NumSlots100PciX:5; // HWINIT
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ULONG:3; // RsvdP
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ULONG NumSlots133PciX:5; // HWINIT
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ULONG:3; // RsvdP
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ULONG NumSlots66Conv:5; // HWINIT
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ULONG:27; // RsvdP
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} SHPC_SLOTS_AVAILABLE_REGISTER, *PSHPC_SLOTS_AVAILABLE_REGISTER;
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//
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// Slot Configuration Register
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//
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typedef struct _SHPC_SLOT_CONFIGURATION_REGISTER {
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ULONG NumSlots:5; // HWINIT
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ULONG:3; // RsvdP
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ULONG FirstDeviceID:5; // HWINIT
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ULONG:3; // RsvdP
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ULONG PhysicalSlotNumber:11; // HWINIT
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ULONG:2; // RsvdP
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ULONG UpDown:1; // HWINIT
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ULONG MRLSensorsImplemented:1; // HWINIT
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ULONG AttentionButtonImplemented:1; // HWINIT
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} SHPC_SLOT_CONFIGURATION_REGISTER, *PSHPC_SLOT_CONFIGURATION_REGISTER;
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//
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// Secondary Bus Configuration Register
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//
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typedef enum _SHPC_BUS_SPEED_MODE {
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SHPC_SPEED_33_CONV = 0,
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SHPC_SPEED_66_CONV,
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SHPC_SPEED_66_PCIX,
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SHPC_SPEED_100_PCIX,
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SHPC_SPEED_133_PCIX
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} SHPC_BUS_SPEED_MODE, *PSHPC_BUS_SPEED_MODE;
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typedef struct _SHPC_BUS_CONFIG_REGISTER {
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ULONG CurrentBusMode:3; // RO SHPC_SPEED_XXX
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ULONG Rsvd:21; // RsvdP
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ULONG ProgIF:8; // RO
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} SHPC_BUS_CONFIG_REGISTER, *PSHPC_BUS_CONFIG_REGISTER;
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//
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// Command Register
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//
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#define SHPC_SLOT_OPERATION_CODE 0x0
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#define SHPC_BUS_SEGMENT_OPERATION_CODE 0x8
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#define SHPC_POWER_ALL_SLOTS_CODE 0x48
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#define SHPC_ENABLE_ALL_SLOTS_CODE 0x49
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//
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// Command defines
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//
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#define IS_COMMAND_SLOT_OPERATION(x) \
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(x.SlotOperation.CommandCode == SHPC_SLOT_OPERATION_CODE)
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#define IS_COMMAND_SET_BUS_SEGMENT(x) \
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(x.BusSegmentOperation.CommandCode == SHPC_BUS_SEGMENT_OPERATION_CODE)
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#define IS_COMMAND_POWER_ALL_SLOTS(x) \
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(x.AsUchar = SHPC_POWER_ALL_SLOTS_CODE)
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#define IS_COMMAND_ENABLE_ALL_SLOTS(x) \
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(x.AsUchar = SHPC_ENABLE_ALL_SLOTS_CODE)
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typedef union _SHPC_CONTROLLER_COMMAND {
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struct {
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UCHAR SlotState:2;
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UCHAR PowerIndicator:2;
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UCHAR AttentionIndicator:2;
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UCHAR CommandCode:2;
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} SlotOperation;
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struct {
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UCHAR BusSpeed:3; // SHPC_SPEED_XXX
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UCHAR CommandCode:5;
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} BusSegmentOperation;
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struct {
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UCHAR Command:6;
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UCHAR CommandCode:2;
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} General;
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UCHAR AsUchar;
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} SHPC_CONTROLLER_COMMAND, *PSHPC_CONTROLLER_COMMAND;
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typedef struct _SHPC_COMMAND_STATUS {
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USHORT ControllerBusy:1; // RO
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USHORT MRLOpen:1; // RO
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USHORT InvalidCommand:1; // RO
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USHORT InvalidSpeedMode:1; // RO
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USHORT Rsvd:12; // RsvdP
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} SHPC_COMMAND_STATUS, *PSHPC_COMMAND_STATUS;
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typedef struct _SHPC_COMMAND_REGISTER {
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SHPC_CONTROLLER_COMMAND Command;
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struct {
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UCHAR TargetForCommand:4;
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UCHAR Rsvd:4; // RsvdP
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} Target;
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SHPC_COMMAND_STATUS Status;
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} SHPC_COMMAND_REGISTER, *PSHPC_COMMAND_REGISTER;
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//
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// Interrupt Locator Register
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//
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typedef struct _SHPC_INT_LOCATOR_REGISTER {
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ULONG CommandCompleteIntPending:1; // RO
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ULONG InterruptLocator:31; // RO
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} SHPC_INT_LOCATOR_REGISTER, *PSHPC_INT_LOCATOR_REGISTER;
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//
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// SERR Locator Register
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//
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typedef struct _SHPC_SERR_LOCATOR_REGISTER {
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ULONG ArbiterSERRPending:1; // RO
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ULONG SERRLocator:31; // RO
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} SHPC_SERR_LOCATOR_REGISTER, *PSHPC_SERR_LOCATOR_REGISTER;
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//
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// Controller SERR-INT Register
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//
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// The low word is the interrupt mask. When mask bits are set, the
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// corresponding operation is masked out.
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//
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#define SHPC_MASK_INT_COMMAND_COMPLETE 0x0001
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#define SHPC_MASK_INT_GLOBAL 0x0002
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#define SHPC_MASK_SERR_GLOBAL 0x0004
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#define SHPC_MASK_SERR_ARBITER_TIMEOUT 0x0008
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// all other bits in the low word are RsvdP
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//
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// The high word is the detected word.
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//
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#define SHPC_DETECTED_COMMAND_COMPLETE 0x0001
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#define SHPC_DETECTED_ARBITER_TIMEOUT 0x0002
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// all other bits in the high word are RsvdZ
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typedef struct _SHPC_SERR_INT_REGISTER {
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USHORT SERRIntMask;
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USHORT SERRIntDetected;
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} SHPC_SERR_INT_REGISTER, *PSHPC_SERR_INT_REGISTER;
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//
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// Slot Specific Registers
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//
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//
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// Status Field
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//
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#define SHPC_SLOT_NOP 0
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#define SHPC_SLOT_POWERED 1
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#define SHPC_SLOT_ENABLED 2
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#define SHPC_SLOT_OFF 3
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#define SHPC_INDICATOR_NOP 0
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#define SHPC_INDICATOR_ON 1
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#define SHPC_INDICATOR_BLINK 2
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#define SHPC_INDICATOR_OFF 3
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#define SHPC_PCIX_NO_CAP 0x0
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#define SHPC_PCIX_66_CAP 0x1
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#define SHPC_PCIX_133_CAP 0x3
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#define SHPC_MRL_CLOSED 0
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#define SHPC_MRL_OPEN 1
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#define SHPC_PRSNT_7_5_WATTS 0
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#define SHPC_PRSNT_25_WATTS 1
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#define SHPC_PRSNT_15_WATTS 2
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#define SHPC_PRSNT_EMPTY 3
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typedef struct _SHPC_SLOT_STATUS_REGISTER {
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USHORT SlotState:2; // SHPC_SLOT_XXX
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USHORT PowerIndicatorState:2; // SHPC_INDICATOR_XXX
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USHORT AttentionIndicatorState:2; // SHPC_INDICATOR_XXX
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USHORT PowerFaultDetected:1;
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USHORT AttentionButtonState:1;
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USHORT MRLSensorState:1; // SHPC_MRL_XXX
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USHORT SpeedCapability:1;
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USHORT PrsntState:2;
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USHORT PCIXCapability:2; //SHPC_PCIX_XXX
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USHORT Rsvd:2;
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} SHPC_SLOT_STATUS_REGISTER, *PSHPC_SLOT_STATUS_REGISTER;
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//
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// Slot Event Latch Field
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//
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// This register is a UCHAR with bit meanings defined
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// below.
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// All undefined bits are RsvdZ
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//
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#define SHPC_SLOT_EVENT_CARD_PRESENCE 0x01
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#define SHPC_SLOT_EVENT_ISO_FAULT 0x02
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#define SHPC_SLOT_EVENT_ATTEN_BUTTON 0x04
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#define SHPC_SLOT_EVENT_MRL_SENSOR 0x08
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#define SHPC_SLOT_EVENT_CONNECT_FAULT 0x10
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#define SHPC_SLOT_EVENT_ALL (SHPC_SLOT_EVENT_CARD_PRESENCE | \
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SHPC_SLOT_EVENT_ISO_FAULT | \
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SHPC_SLOT_EVENT_ATTEN_BUTTON | \
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SHPC_SLOT_EVENT_MRL_SENSOR | \
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SHPC_SLOT_EVENT_CONNECT_FAULT)
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//
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// Slot INT-SERR Mask Field
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//
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// This register is a UCHAR with bit meanings defined below
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// All undefined bits are RsvdP
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//
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#define SHPC_SLOT_INT_CARD_PRESENCE 0x01
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#define SHPC_SLOT_INT_ISO_FAULT 0x02
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#define SHPC_SLOT_INT_ATTEN_BUTTON 0x04
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#define SHPC_SLOT_INT_MRL_SENSOR 0x08
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#define SHPC_SLOT_INT_CONNECT_FAULT 0x10
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#define SHPC_SLOT_SERR_MRL_SENSOR 0x20
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#define SHPC_SLOT_SERR_CONNECT_FAULT 0x40
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#define SHPC_SLOT_INT_ALL (SHPC_SLOT_INT_CARD_PRESENCE | \
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SHPC_SLOT_INT_ISO_FAULT | \
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SHPC_SLOT_INT_ATTEN_BUTTON | \
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SHPC_SLOT_INT_MRL_SENSOR | \
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SHPC_SLOT_INT_CONNECT_FAULT)
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#define SHPC_SLOT_SERR_ALL (SHPC_SLOT_SERR_CONNECT_FAULT | \
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SHPC_SLOT_SERR_MRL_SENSOR)
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//
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// Overall Slot Register structure
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//
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typedef struct _SHPC_SLOT_REGISTER {
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SHPC_SLOT_STATUS_REGISTER SlotStatus; //RO
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UCHAR SlotEventLatch;
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UCHAR IntSERRMask;
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} SHPC_SLOT_REGISTER, *PSHPC_SLOT_REGISTER;
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//
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// Overall Register Set Structures
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//
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#define SHPC_MAX_SLOT_REGISTERS 31
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typedef struct _SHPC_WORKING_REGISTERS {
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ULONG BaseOffset;
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SHPC_SLOTS_AVAILABLE_REGISTER SlotsAvailable;
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SHPC_SLOT_CONFIGURATION_REGISTER SlotConfig;
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SHPC_BUS_CONFIG_REGISTER BusConfig;
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SHPC_COMMAND_REGISTER Command;
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SHPC_INT_LOCATOR_REGISTER IntLocator;
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SHPC_SERR_LOCATOR_REGISTER SERRLocator;
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SHPC_SERR_INT_REGISTER SERRInt;
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SHPC_SLOT_REGISTER SlotRegisters[SHPC_MAX_SLOT_REGISTERS];
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} SHPC_WORKING_REGISTERS, *PSHPC_WORKING_REGISTERS;
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//
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// Register access structures and defines
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//
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#define SHPC_NUM_REGISTERS sizeof(SHPC_WORKING_REGISTERS)/sizeof(ULONG)
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#define SHPC_FIRST_SLOT_REG (SHPC_NUM_REGISTERS - SHPC_MAX_SLOT_REGISTERS)
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typedef union _SHPC_REGISTER_SET {
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SHPC_WORKING_REGISTERS WorkingRegisters;
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ULONG AsULONGs[SHPC_NUM_REGISTERS];
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} SHPC_REGISTER_SET, *PSHPC_REGISTER_SET;
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//
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// HBRB defines
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//
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#define HBRB_PACKAGE_COUNT 2
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typedef struct _HBRB_HEADER {
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USHORT VendorID;
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USHORT DeviceID;
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UCHAR RevisionID;
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UCHAR ProgIF;
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UCHAR BusNumber;
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UCHAR HBRBVersion;
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USHORT SubVendorID;
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USHORT SubSystemID;
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ULONG Size;
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ULONG CapabilitiesPtr;
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} HBRB_HEADER, *PHBRB_HEADER;
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typedef struct _HBRB_CAPABILITIES_HEADER {
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ULONG CapabilityID;
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ULONG Next;
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} HBRB_CAPABILITIES_HEADER, *PHBRB_CAPABILITIES_HEADER;
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typedef struct _HBRB_CAPABILITY {
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HBRB_CAPABILITIES_HEADER Header;
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SHPC_WORKING_REGISTERS RegisterSet;
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} SHPC_HBRB_CAPABILITY, *PSHPC_HBRB_CAPABILITY;
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//
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// SHPC config space defines
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//
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typedef union _SHPC_CONFIG_PENDING {
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struct {
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|
UCHAR ControllerSERRPending:1; // RO
|
||
|
|
UCHAR ControllerIntPending:1; // RO
|
||
|
|
UCHAR:6; // RsvdP
|
||
|
|
|
||
|
|
} Field;
|
||
|
|
|
||
|
|
UCHAR AsUCHAR;
|
||
|
|
|
||
|
|
} SHPC_CONFIG_PENDING, *PSHPC_CONFIG_PENDING;
|
||
|
|
|
||
|
|
typedef struct _SHPC_CONFIG_SPACE {
|
||
|
|
|
||
|
|
PCI_CAPABILITIES_HEADER Header; //RO
|
||
|
|
|
||
|
|
UCHAR DwordSelect;
|
||
|
|
SHPC_CONFIG_PENDING Pending;
|
||
|
|
|
||
|
|
ULONG Data;
|
||
|
|
|
||
|
|
} SHPC_CONFIG_SPACE, *PSHPC_CONFIG_SPACE;
|
||
|
|
|
||
|
|
#include "poppack.h"
|
||
|
|
|
||
|
|
#define SHPC_CAPABILITY_ID 0xC
|
||
|
|
|
||
|
|
//
|
||
|
|
// Bit type masks
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// XxxRO indicates the mask of bits in the register that are Read Only
|
||
|
|
// XxxRW indicates the mask of bits in the register that are Read Write
|
||
|
|
// XxxRWC indicates the mask of bits in the register that are Read/Write Clear
|
||
|
|
// XxxRsvdP indicates the mask of bits in the register that are Reserved
|
||
|
|
// and whose values should be preserved on writes.
|
||
|
|
// XxxRsvdZ indicates the mask of bits in the register that are Reserved
|
||
|
|
// and whose values should be always written as zeros.
|
||
|
|
//
|
||
|
|
// All of the listed masks for a register should always add to 0xFFFFFFFF
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Base Offset Register
|
||
|
|
//
|
||
|
|
#define BaseOffsetRO 0xFFFFFFFF
|
||
|
|
|
||
|
|
//
|
||
|
|
// Slots Available Registers
|
||
|
|
// DWord1 is the lower dword
|
||
|
|
// DWord2 is the upper dword
|
||
|
|
//
|
||
|
|
#define SlotsAvailDWord1RO 0x1F1F1F1F
|
||
|
|
#define SlotsAvailDWord1RsvdP 0xE0E0E0E0
|
||
|
|
|
||
|
|
#define SlotsAvailDWord2RO 0x0000001F
|
||
|
|
#define SlotsAvailDWord2RsvdP 0xFFFFFFE0
|
||
|
|
|
||
|
|
//
|
||
|
|
// Slot Configuration Register
|
||
|
|
//
|
||
|
|
#define SlotConfigRO 0xE7FF1F1F
|
||
|
|
#define SlotConfigRsvdP 0x1800E0E0
|
||
|
|
|
||
|
|
//
|
||
|
|
// Secondary Bus Configuration Register
|
||
|
|
// This mask includes the SHPC Programming Interface register
|
||
|
|
//
|
||
|
|
#define BusConfigRO 0xFF000007
|
||
|
|
#define BusConfigRsvdP 0x00FFFFF8
|
||
|
|
|
||
|
|
//
|
||
|
|
// Controller Command/Status Register
|
||
|
|
// This mask includes both the Command and Command Status registers
|
||
|
|
//
|
||
|
|
#define CommandStatusRO 0x000F0000
|
||
|
|
#define CommandStatusRW 0x00001FFF
|
||
|
|
#define CommandStatusRsvdP 0xFFF0E000
|
||
|
|
|
||
|
|
//
|
||
|
|
// Interrupt Locator Register
|
||
|
|
//
|
||
|
|
#define IntLocatorRO 0xFFFFFFFF
|
||
|
|
|
||
|
|
//
|
||
|
|
// SERR Locator Register
|
||
|
|
//
|
||
|
|
#define SERRLocatorRO 0xFFFFFFFF
|
||
|
|
|
||
|
|
//
|
||
|
|
// Controller SERR-INT Register
|
||
|
|
//
|
||
|
|
#define ControllerMaskRW 0x0000000F
|
||
|
|
#define ControllerMaskRWC 0x00030000
|
||
|
|
#define ControllerMaskRsvdP 0x0000FFF0
|
||
|
|
#define ControllerMaskRsvdZ 0xFFFC0000
|
||
|
|
|
||
|
|
//
|
||
|
|
// Slot Specific Registers
|
||
|
|
//
|
||
|
|
#define SlotRO 0x00003FFF
|
||
|
|
#define SlotRW 0x7F000000
|
||
|
|
#define SlotRWC 0x001F0000
|
||
|
|
#define SlotRsvdP 0x80000000
|
||
|
|
#define SlotRsvdZ 0x00E0C000
|
||
|
|
|
||
|
|
#endif
|