Brandon Wright
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a19395ee3c
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Start converting some opcodes to cycle-based.
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2011-09-14 12:54:51 -05:00 |
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Brandon Wright
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4668ae5850
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Fix save state error.
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2011-09-07 11:46:52 -05:00 |
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Brandon Wright
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baa4de3713
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Save a few more mmapped registers to SPC files. Fix key-on trigger.
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2011-07-05 14:05:36 -05:00 |
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Brandon Wright
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2b5a54b401
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Inline ticks. This should fix speed issues.
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2011-07-05 06:23:24 -05:00 |
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Brandon Wright
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63b0a6d45e
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Add DSP clock remainder to save state.
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2011-07-04 17:33:09 -05:00 |
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Brandon Wright
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91e69af029
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Loosen SMP<->DSP synchronization.
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2011-06-27 15:41:17 -05:00 |
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Brandon Wright
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ebc9e721f6
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Add SPC dumping support.
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2011-06-26 05:33:14 -05:00 |
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Brandon Wright
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2e94b98e90
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Clear up CYCLE_ACCURATE confusion. Rename dsp.* to sdsp.*.
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2011-06-25 03:10:42 -05:00 |
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Brandon Wright
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39add9b47e
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Save states support for new APU.
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2011-06-24 06:42:04 -05:00 |
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Brandon Wright
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08f5601c5f
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Reduce the sync footprint slightly with less indirection.
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2011-06-23 06:14:14 -05:00 |
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Brandon Wright
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ebc9b70860
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Fix permissions.
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2011-06-23 05:29:04 -05:00 |
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Brandon Wright
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1af39f3845
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Clean things up slightly. Switch CYCLE_ACCURATE off, since things seem
to work fine without it.
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2011-06-23 05:24:13 -05:00 |
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Brandon Wright
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5d5eaedd5e
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New SMP is tentatively "running" now.
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2011-06-22 06:03:29 -05:00 |
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Brandon Wright
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10a521e39c
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byuu APU now being used. Nothing works yet.
Sync is broken, but the new SMP will handle ratios now.
Save states need to be redone without serializer.
No SPC dumping.
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2011-06-18 05:31:44 -05:00 |
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Brandon Wright
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c9c49095ee
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Add byuu's SMP and DSP files to tree.
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2011-06-12 01:25:22 -05:00 |
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